Low Power and Area Efficient 64 Bit Arithmetic Logical Unit Design

Authors:

P S. Surekha , Amandu Swathi , K. Shravani , A. Srinivas , P. Aravind

Page No: 277-293

Abstract:

The adders, multipliers are the essential building blocks for every integrated circuit (IC) and especially for Arithmetic and Logical units (ALU). Thus, the design of adders and multipliers must inhibit the area, delay and power efficient properties. But most of the conventional adders are failed to provide these properties in multipliers andALUs implementation.

Description:

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Volume & Issue

Volume-10,ISSUE-5

Keywords

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